1. Field of the Invention
The subject invention is generally related to the discretionary formation of electrical contacts to semiconductor or other structures containing patterned metal areas and, more particularly, to an automated process which differentiates acceptable structures from unacceptable structures according to predefined parameters and then selectively connects only the acceptable structures.
2. Description of the Prior Art
As is well known in the art, the yield from conventional processes for fabricating metal oxide semiconductor (MOS) devices is considerably less than 100%. Specific examples of MOS devices in common use include MOS controlled thyristors (MCTs), metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). If multiple devices are connected in a parallel circuit and one of those devices is shorted, for example a conductive rum connecting the drain and source in a MOSFET, the entire circuit will not function properly. In order to obtain the highest yield of acceptable parallel circuit arrays, it is imperative that only "good" devices be interconnected. Various methods for the discretionary interconnection of semiconductor devices are known in the art.
In "Active Memory Calls for Discretion", by Canning et al. Electronics, Feb. 20, 1967, pp. 143 to 154, a discretionary wiring approach which assures high yield in 1600-bit memory slices is disclosed. In discretionary wiring, each cell is tested prior to interconnection, and only the "good" circuits are used in the final array. Good and bad cells on the slice are determined by an automatically stepped multipoint probe controlled by a computer. A unique discretionary interconnection pattern is determined by the computer utilizing the test data. The pattern bypasses defective cells on the slice. The pattern is input into a multilevel interconnection generator (MIG) in which a computer controlled cathode ray tube beam generates the required pattern on film forming a mask. The mask is then used to form the interconnection pattern.
U.S. Pat. No. 3,702,025 to Archer discloses a simplified discretionary interconnection process wherein numerous identical or similar cells are formed into a continuous chain of such cells on a single semiconductor wafer. The cells are cataloged as either good or bad cells using a test probe and recording means. The cells are then covered with a dielectric layer and a second layer connection pattern is formed. Connections are made to contacts on the good cells only, with the connection pattern skipping across defective cells.
In the cross-referenced patent application, a plurality of substantially identical semiconductor devices such as MOSFETs are formed on a single wafer. The devices are individually tested and categorized as acceptable or unacceptable depending on preselected parameters. Only the acceptable devices are coupled together in parallel to form a parallel array by a process which involves overcoating the device contacts with a suitable insulating coating such as two spin coated dielectric layers, selectively forming openings through the insulating coating using laser drilling to the pads of the acceptable devices, and depositing a metallization layer over the coating and through the openings to contact the pads of acceptable devices. The metallization layer is then patterned to form separate conductive runs, one for each set of similar contact pads on the devices, each set of contact pads corresponding to a different active semiconductor region of each device. A preselected number of arrays are coupled in parallel to form a mosaic having the desired power rating.
The prior art for discretionary interconnections requires that the acceptable devices be identified first, so that patterns can then be formed to interconnect only those devices. The prior art does not show the identification of defective devices followed by the application of a means to prevent those defective devices from being incorporated into a resulting circuit.